The fabrication of semiconductor devices, such as logic and memory devices, typically includes a large number of processing steps to form various features and multiple layers. For example, layers may be formed with a lithography process. Lithography is performed by transferring a pattern from a reticle to a resist arranged on a semiconductor substrate. Metrology processes may be used between lithography processing steps, or any other processing steps, in order to monitor the accuracy of the semiconductor fabrication. For example, metrology processes may measure one or more characteristics of a wafer such as the dimensions (e.g., line width, thickness, etc.) of features formed on the wafer during a process step. Overlay error is an example of a characteristic that is of critical importance. An overlay measurement generally specifies how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it or how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. The overlay error is typically determined with an overlay target having structures formed on one or more layers of the semiconductor substrate. If the two layers or patterns are properly formed, then the structure on one layer or pattern tends to be aligned with the structure on the other layer or pattern. If the two layers or patterns are not properly formed, then the structure on one layer or pattern tends to be offset or misaligned relative to the structure on the other layer or pattern.
The overlay error can be separated into two components: (1) random errors; and (2) systematic errors. Random errors, such as precision, may be averaged out through measurement of an adequately large sample size. However, the systematic errors cannot be removed through the use of averaging, because they are the result of inherent biases in a target, the substrate itself, the measurement tool, or any combination thereof. For example, a target may have an asymmetrical shape that influences the accuracy of the overlay error. A detailed description of the effect asymmetrical shape has on the overlay error is provided in commonly owned U.S. patent application Ser. No. 13/508,495, entitled METHOD AND SYSTEM FOR PROVIDING A QUALITY METRIC FOR IMPROVED PROCESS CONTROL, filed May 7, 2012, by Daniel Kandel et al. which is incorporated herein in its entirety.
As a result, it is desirable to provide a system and method suitable for mitigating the impact of the systematic overlay errors. It is within this context that embodiments of the present invention arise.